sc2210.c.bak 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * sc2210 driver
  4. *
  5. * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
  6. *
  7. * V0.0X01.0X01 first version
  8. */
  9. //#define DEBUG
  10. #include <linux/clk.h>
  11. #include <linux/device.h>
  12. #include <linux/delay.h>
  13. #include <linux/gpio/consumer.h>
  14. #include <linux/i2c.h>
  15. #include <linux/module.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/sysfs.h>
  19. #include <linux/slab.h>
  20. #include <linux/version.h>
  21. #include <linux/rk-camera-module.h>
  22. #include <linux/rk-preisp.h>
  23. #include <media/media-entity.h>
  24. #include <media/v4l2-async.h>
  25. #include <media/v4l2-ctrls.h>
  26. #include <media/v4l2-subdev.h>
  27. #include <linux/pinctrl/consumer.h>
  28. #include "../platform/rockchip/isp/rkisp_tb_helper.h"
  29. #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
  30. #ifndef V4L2_CID_DIGITAL_GAIN
  31. #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
  32. #endif
  33. #define sc2210_LANES (2LL)
  34. #define sc2210_BITS_PER_SAMPLE (10LL)
  35. //#define sc2210_LINK_FREQ_405 432000000LL
  36. //186000000
  37. //202500000LL
  38. //#define sc2210_LINK_FREQ_405 (200000000LL)
  39. // 798M : can not get any video
  40. // 250M :
  41. #define sc2210_LINK_FREQ_405 (200000000LL)
  42. #define PIXEL_RATE_WITH_405M_10BIT (sc2210_LINK_FREQ_405 * 2LL * sc2210_LANES / sc2210_BITS_PER_SAMPLE)
  43. #define CHIP_ID 0x2210
  44. #define sc2210_REG_CHIP_ID 0x3107
  45. #define sc2210_REG_CTRL_MODE 0x0100
  46. #define sc2210_MODE_SW_STANDBY 0x0
  47. #define sc2210_MODE_STREAMING BIT(0)
  48. #define sc2210_REG_EXPOSURE_H 0x3e00
  49. #define sc2210_REG_EXPOSURE_M 0x3e01
  50. #define sc2210_REG_EXPOSURE_L 0x3e02
  51. #define sc2210_EXPOSURE_MIN 1
  52. #define sc2210_EXPOSURE_STEP 1
  53. #define sc2210_VTS_MAX 0x7fff
  54. #define sc2210_REG_DIG_GAIN 0x3e06
  55. #define sc2210_REG_DIG_FINE_GAIN 0x3e07
  56. #define sc2210_REG_ANA_GAIN 0x3e09
  57. #define sc2210_GAIN_MIN 0x0020
  58. #define sc2210_GAIN_MAX (4096) //32*4*32
  59. #define sc2210_GAIN_STEP 1
  60. #define sc2210_GAIN_DEFAULT 0x80
  61. //#define sc2210_REG_GROUP_HOLD 0x3812
  62. //#define sc2210_GROUP_HOLD_START 0x00
  63. //#define sc2210_GROUP_HOLD_END 0x30
  64. #define sc2210_REG_TEST_PATTERN 0x4501
  65. #define sc2210_TEST_PATTERN_BIT_MASK BIT(3)
  66. #define sc2210_REG_VTS_H 0x320e
  67. #define sc2210_REG_VTS_L 0x320f
  68. #define sc2210_FLIP_MIRROR_REG 0x3221
  69. #define sc2210_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
  70. #define sc2210_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
  71. #define sc2210_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
  72. #define sc2210_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
  73. #define sc2210_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
  74. #define sc2210_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
  75. #define sc2210_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
  76. #define REG_DELAY 0xFFFE
  77. #define REG_NULL 0xFFFF
  78. #define sc2210_REG_VALUE_08BIT 1
  79. #define sc2210_REG_VALUE_16BIT 2
  80. #define sc2210_REG_VALUE_24BIT 3
  81. #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
  82. #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
  83. #define sc2210_NAME "sc2210"
  84. static const char * const sc2210_supply_names[] = {
  85. "avdd", /* Analog power */
  86. "dovdd", /* Digital I/O power */
  87. "dvdd", /* Digital core power */
  88. };
  89. #define sc2210_NUM_SUPPLIES ARRAY_SIZE(sc2210_supply_names)
  90. struct regval {
  91. u16 addr;
  92. u8 val;
  93. };
  94. struct sc2210_mode {
  95. u32 bus_fmt;
  96. u32 width;
  97. u32 height;
  98. struct v4l2_fract max_fps;
  99. u32 hts_def;
  100. u32 vts_def;
  101. u32 exp_def;
  102. const struct regval *reg_list;
  103. u32 hdr_mode;
  104. u32 xvclk_freq;
  105. u32 link_freq_idx;
  106. u32 vc[PAD_MAX];
  107. };
  108. struct sc2210 {
  109. struct i2c_client *client;
  110. struct clk *xvclk;
  111. struct gpio_desc *reset_gpio;
  112. struct regulator_bulk_data supplies[sc2210_NUM_SUPPLIES];
  113. struct pinctrl *pinctrl;
  114. struct pinctrl_state *pins_default;
  115. struct pinctrl_state *pins_sleep;
  116. struct v4l2_subdev subdev;
  117. struct media_pad pad;
  118. struct v4l2_ctrl_handler ctrl_handler;
  119. struct v4l2_ctrl *exposure;
  120. struct v4l2_ctrl *anal_gain;
  121. struct v4l2_ctrl *digi_gain;
  122. struct v4l2_ctrl *hblank;
  123. struct v4l2_ctrl *vblank;
  124. struct v4l2_ctrl *pixel_rate;
  125. struct v4l2_ctrl *link_freq;
  126. struct v4l2_ctrl *test_pattern;
  127. struct mutex mutex;
  128. bool streaming;
  129. bool power_on;
  130. const struct sc2210_mode *cur_mode;
  131. u32 module_index;
  132. const char *module_facing;
  133. const char *module_name;
  134. const char *len_name;
  135. u32 cur_vts;
  136. bool has_init_exp;
  137. bool is_thunderboot;
  138. bool is_first_streamoff;
  139. struct preisp_hdrae_exp_s init_hdrae_exp;
  140. };
  141. #define to_sc2210(sd) container_of(sd, struct sc2210, subdev)
  142. /*
  143. * Xclk 24Mhz
  144. */
  145. static const struct regval sc2210_global_regs[] = {
  146. {REG_NULL, 0x00},
  147. };
  148. /*
  149. 1080p_25p
  150. */
  151. static const struct regval sc2210_linear_10_1920x1080_30fps_regs[] = {
  152. {0x0100,0x00},
  153. {0x0100,0x00},
  154. {0x0100,0x00},
  155. {0x0103,0x01}, //reset
  156. {0x0100,0x00},
  157. {0x0100,0x00},
  158. {0x0100,0x00},
  159. {0x0100,0x00},
  160. {0x0100,0x00},
  161. {0x36e9,0x80},
  162. {0x36f9,0x80},
  163. {0x3001,0x07},
  164. {0x3002,0xc0},
  165. {0x300a,0x2c},
  166. {0x300f,0x00},
  167. {0x3018,0x33},
  168. {0x3019,0x0c},
  169. {0x301f,0x47},
  170. {0x3031,0x0a},
  171. {0x3033,0x20},
  172. {0x3038,0x22},
  173. {0x3106,0x81},
  174. {0x3201,0x04},
  175. {0x3203,0x04},
  176. {0x3204,0x07},
  177. {0x3205,0x8b},
  178. {0x3206,0x04},
  179. {0x3207,0x43},
  180. {0x320c,0x04},
  181. {0x320d,0x4c},
  182. {0x320e,0x05}, //sc2210_REG_VTS_H
  183. {0x320f,0x46},//25fps sc2210_REG_VTS_L
  184. {0x3211,0x04}, //输出窗口列起始位置
  185. {0x3213,0x04}, //输出窗口行起始位置
  186. {0x3231,0x02},
  187. {0x3253,0x04},
  188. {0x3301,0x0a},
  189. {0x3302,0x10},
  190. {0x3304,0x48},
  191. {0x3305,0x00},
  192. {0x3306,0x68},
  193. {0x3308,0x20},
  194. {0x3309,0x98},
  195. {0x330a,0x00},
  196. {0x330b,0xe8},
  197. {0x330e,0x68},
  198. {0x3314,0x92},
  199. {0x3000,0xc0},
  200. {0x331e,0x41},
  201. {0x331f,0x91},
  202. {0x334c,0x10},
  203. {0x335d,0x60},
  204. {0x335e,0x02},
  205. {0x335f,0x06},
  206. {0x3364,0x16},
  207. {0x3366,0x92},
  208. {0x3367,0x10},
  209. {0x3368,0x04},
  210. {0x3369,0x00},
  211. {0x336a,0x00},
  212. {0x336b,0x00},
  213. {0x336d,0x03},
  214. {0x337c,0x08},
  215. {0x337d,0x0e},
  216. {0x337f,0x33},
  217. {0x3390,0x10},
  218. {0x3391,0x30},
  219. {0x3392,0x40},
  220. {0x3393,0x0a},
  221. {0x3394,0x0a},
  222. {0x3395,0x0a},
  223. {0x3396,0x08},
  224. {0x3397,0x30},
  225. {0x3398,0x3f},
  226. {0x3399,0x50},
  227. {0x339a,0x50},
  228. {0x339b,0x50},
  229. {0x339c,0x50},
  230. {0x33a2,0x0a},
  231. {0x33b9,0x0e},
  232. {0x33e1,0x08},
  233. {0x33e2,0x18},
  234. {0x33e3,0x18},
  235. {0x33e4,0x18},
  236. {0x33e5,0x10},
  237. {0x33e6,0x06},
  238. {0x33e7,0x02},
  239. {0x33e8,0x18},
  240. {0x33e9,0x10},
  241. {0x33ea,0x0c},
  242. {0x33eb,0x10},
  243. {0x33ec,0x04},
  244. {0x33ed,0x02},
  245. {0x33ee,0xa0},
  246. {0x33ef,0x08},
  247. {0x33f4,0x18},
  248. {0x33f5,0x10},
  249. {0x33f6,0x0c},
  250. {0x33f7,0x10},
  251. {0x33f8,0x06},
  252. {0x33f9,0x02},
  253. {0x33fa,0x18},
  254. {0x33fb,0x10},
  255. {0x33fc,0x0c},
  256. {0x33fd,0x10},
  257. {0x33fe,0x04},
  258. {0x33ff,0x02},
  259. {0x360f,0x01},
  260. {0x3622,0xf7},
  261. {0x3625,0x0a},
  262. {0x3627,0x02},
  263. {0x3630,0xa2},
  264. {0x3631,0x00},
  265. {0x3632,0xd8},
  266. {0x3633,0x33},
  267. {0x3635,0x20},
  268. {0x3638,0x24},
  269. {0x363a,0x80},
  270. {0x363b,0x02},
  271. {0x363e,0x22},
  272. {0x3670,0x40},
  273. {0x3671,0xf7},
  274. {0x3672,0xf7},
  275. {0x3673,0x07},
  276. {0x367a,0x40},
  277. {0x367b,0x7f},
  278. {0x36b5,0x40},
  279. {0x36b6,0x7f},
  280. {0x36c0,0x80},
  281. {0x36c1,0x9f},
  282. {0x36c2,0x9f},
  283. {0x36cc,0x22},
  284. {0x36cd,0x23},
  285. {0x36ce,0x30},
  286. {0x36d0,0x20},
  287. {0x36d1,0x40},
  288. {0x36d2,0x7f},
  289. {0x36ea,0x75},
  290. {0x36eb,0x0d},
  291. {0x36ec,0x13},
  292. {0x36ed,0x24},
  293. {0x36fa,0x5f},
  294. {0x36fb,0x1b},
  295. {0x36fc,0x10},
  296. {0x36fd,0x07},
  297. {0x3905,0xd8},
  298. {0x3907,0x01},
  299. {0x3908,0x11},
  300. {0x391b,0x83},
  301. {0x391d,0x2c},
  302. {0x391f,0x00},
  303. {0x3933,0x28},
  304. {0x3934,0xa6},
  305. {0x3940,0x70},
  306. {0x3942,0x08},
  307. {0x3943,0xbc},
  308. {0x3958,0x02},
  309. {0x3959,0x04},
  310. {0x3980,0x61},
  311. {0x3987,0x0b},
  312. {0x3990,0x00},
  313. {0x3991,0x00},
  314. {0x3992,0x00},
  315. {0x3993,0x00},
  316. {0x3994,0x00},
  317. {0x3995,0x00},
  318. {0x3996,0x00},
  319. {0x3997,0x00},
  320. {0x3998,0x00},
  321. {0x3999,0x00},
  322. {0x399a,0x00},
  323. {0x399b,0x00},
  324. {0x399c,0x00},
  325. {0x399d,0x00},
  326. {0x399e,0x00},
  327. {0x399f,0x00},
  328. {0x39a0,0x00},
  329. {0x39a1,0x00},
  330. {0x39a2,0x03},
  331. {0x39a3,0x30},
  332. {0x39a4,0x03},
  333. {0x39a5,0x60},
  334. {0x39a6,0x03},
  335. {0x39a7,0xa0},
  336. {0x39a8,0x03},
  337. {0x39a9,0xb0},
  338. {0x39aa,0x00},
  339. {0x39ab,0x00},
  340. {0x39ac,0x00},
  341. {0x39ad,0x20},
  342. {0x39ae,0x00},
  343. {0x39af,0x40},
  344. {0x39b0,0x00},
  345. {0x39b1,0x60},
  346. {0x39b2,0x00},
  347. {0x39b3,0x00},
  348. {0x39b4,0x08},
  349. {0x39b5,0x14},
  350. {0x39b6,0x20},
  351. {0x39b7,0x38},
  352. {0x39b8,0x38},
  353. {0x39b9,0x20},
  354. {0x39ba,0x14},
  355. {0x39bb,0x08},
  356. {0x39bc,0x08},
  357. {0x39bd,0x10},
  358. {0x39be,0x20},
  359. {0x39bf,0x30},
  360. {0x39c0,0x30},
  361. {0x39c1,0x20},
  362. {0x39c2,0x10},
  363. {0x39c3,0x08},
  364. {0x39c4,0x00},
  365. {0x39c5,0x80},
  366. {0x39c6,0x00},
  367. {0x39c7,0x80},
  368. {0x39c8,0x00},
  369. {0x39c9,0x00},
  370. {0x39ca,0x80},
  371. {0x39cb,0x00},
  372. {0x39cc,0x00},
  373. {0x39cd,0x00},
  374. {0x39ce,0x00},
  375. {0x39cf,0x00},
  376. {0x39d0,0x00},
  377. {0x39d1,0x00},
  378. {0x39e2,0x05},
  379. {0x39e3,0xeb},
  380. {0x39e4,0x07},
  381. {0x39e5,0xb6},
  382. {0x39e6,0x00},
  383. {0x39e7,0x3a},
  384. {0x39e8,0x3f},
  385. {0x39e9,0xb7},
  386. {0x39ea,0x02},
  387. {0x39eb,0x4f},
  388. {0x39ec,0x08},
  389. {0x39ed,0x00},
  390. {0x3e01,0x46},
  391. {0x3e02,0x10},
  392. {0x3e09,0x40},
  393. {0x3e14,0x31},
  394. {0x3e1b,0x3a},
  395. {0x3e26,0x40},
  396. {0x4401,0x1a},
  397. {0x4407,0xc0},
  398. {0x4418,0x34},
  399. {0x4500,0x18},
  400. {0x4501,0xb4}, //test patten 0xb4
  401. {0x4509,0x20},
  402. {0x4603,0x00},
  403. {0x4800,0x24},
  404. {0x4837,0x2b},
  405. {0x5000,0x0e},
  406. {0x550f,0x20},
  407. {0x36e9,0x51},
  408. {0x36f9,0x53},
  409. //{0x0100,0x01},
  410. {REG_NULL, 0x00},
  411. };
  412. static const struct sc2210_mode supported_modes[] = {
  413. {
  414. .width = 1920,
  415. .height = 1080,
  416. .max_fps = {
  417. .numerator = 10000,
  418. .denominator = 250000,
  419. },
  420. .exp_def = 0x80, //0x080
  421. .hts_def = (1100),
  422. .vts_def = (0x546), //0x546
  423. .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10, //MEDIA_BUS_FMT_SBGGR10_1X10
  424. .reg_list = sc2210_linear_10_1920x1080_30fps_regs,
  425. .hdr_mode = NO_HDR,
  426. .xvclk_freq = 27000000,
  427. .link_freq_idx = 0,
  428. .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
  429. },
  430. };
  431. static const s64 link_freq_menu_items[] = {
  432. sc2210_LINK_FREQ_405,
  433. };
  434. static const char * const sc2210_test_pattern_menu[] = {
  435. "Disabled",
  436. "Vertical Color Bar Type 1",
  437. "Vertical Color Bar Type 2",
  438. "Vertical Color Bar Type 3",
  439. "Vertical Color Bar Type 4",
  440. };
  441. /* Write registers up to 4 at a time */
  442. static int sc2210_write_reg(struct i2c_client *client, u16 reg,
  443. u32 len, u32 val)
  444. {
  445. u32 buf_i, val_i;
  446. u8 buf[6];
  447. u8 *val_p;
  448. __be32 val_be;
  449. if (len > 4)
  450. return -EINVAL;
  451. buf[0] = reg >> 8;
  452. buf[1] = reg & 0xff;
  453. val_be = cpu_to_be32(val);
  454. val_p = (u8 *)&val_be;
  455. buf_i = 2;
  456. val_i = 4 - len;
  457. while (val_i < 4)
  458. buf[buf_i++] = val_p[val_i++];
  459. if (i2c_master_send(client, buf, len + 2) != len + 2)
  460. {
  461. printk("i2c_master_send error\n");
  462. return -EIO;
  463. }
  464. printk("sc2210_write_reg! addr=0x%X val=0x%X len=%d \n",reg,val,len);
  465. return 0;
  466. }
  467. static int isc2210_write_reg(struct i2c_client *client, u16 reg,
  468. u32 len, u32 val)
  469. {
  470. u32 buf_i, val_i;
  471. u8 buf[6];
  472. u8 *val_p;
  473. __be32 val_be;
  474. if (len > 4)
  475. return -EINVAL;
  476. buf[0] = reg >> 8;
  477. buf[1] = reg & 0xff;
  478. val_be = cpu_to_be32(val);
  479. val_p = (u8 *)&val_be;
  480. buf_i = 2;
  481. val_i = 4 - len;
  482. while (val_i < 4)
  483. buf[buf_i++] = val_p[val_i++];
  484. if (i2c_master_send(client, buf, len + 2) != len + 2)
  485. {
  486. printk("i2c_master_send error\n");
  487. return -EIO;
  488. }
  489. // printk("sc2210_write_reg! addr=0x%X val=0x%X len=%d \n",reg,val,len);
  490. return 0;
  491. }
  492. static int sc2210_write_array(struct i2c_client *client,
  493. const struct regval *regs)
  494. {
  495. u32 i;
  496. int ret = 0;
  497. for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
  498. ret = isc2210_write_reg(client, regs[i].addr,
  499. sc2210_REG_VALUE_08BIT, regs[i].val);
  500. printk("sc2210_write_array! i=%d \n",i);
  501. return ret;
  502. }
  503. /* Read registers up to 4 at a time */
  504. static int sc2210_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
  505. u32 *val)
  506. {
  507. struct i2c_msg msgs[2];
  508. u8 *data_be_p;
  509. __be32 data_be = 0;
  510. __be16 reg_addr_be = cpu_to_be16(reg);
  511. int ret;
  512. if (len > 4 || !len)
  513. return -EINVAL;
  514. data_be_p = (u8 *)&data_be;
  515. /* Write register address */
  516. msgs[0].addr = client->addr;
  517. msgs[0].flags = 0;
  518. msgs[0].len = 2;
  519. msgs[0].buf = (u8 *)&reg_addr_be;
  520. /* Read data from register */
  521. msgs[1].addr = client->addr;
  522. msgs[1].flags = I2C_M_RD;
  523. msgs[1].len = len;
  524. msgs[1].buf = &data_be_p[4 - len];
  525. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  526. if (ret != ARRAY_SIZE(msgs))
  527. return -EIO;
  528. *val = be32_to_cpu(data_be);
  529. return 0;
  530. }
  531. static int sc2210_set_gain_reg(struct sc2210 *sc2210, u32 gain)
  532. {
  533. u32 coarse_again = 0, coarse_dgain = 0, fine_dgain = 0;
  534. u32 gain_factor;
  535. int ret = 0;
  536. return ret; //debug ws
  537. gain_factor = gain * 1000 / 32;
  538. if (gain_factor < 1000) {
  539. coarse_again = 0x00;
  540. coarse_dgain = 0x00;
  541. fine_dgain = 0x80;
  542. } else if (gain_factor < 1000 * 2) { /*1x ~ 2x gain*/
  543. coarse_again = 0x00;
  544. coarse_dgain = 0x00;
  545. fine_dgain = gain_factor * 128 / 1000;
  546. } else if (gain_factor < 1000 * 4) { /*2x ~ 4x gain*/
  547. coarse_again = 0x01;
  548. coarse_dgain = 0x00;
  549. fine_dgain = gain_factor * 128 / 1000 / 2;
  550. } else if (gain_factor < 1000 * 8) { /*4x ~ 8x gain*/
  551. coarse_again = 0x03;
  552. coarse_dgain = 0x00;
  553. fine_dgain = gain_factor * 128 / 1000 / 4;
  554. } else if (gain_factor < 1000 * 16) { /*8x ~ 16x gain*/
  555. coarse_again = 0x07;
  556. coarse_dgain = 0x00;
  557. fine_dgain = gain_factor * 128 / 1000 / 8;
  558. } else if (gain_factor < 1000 * 32) { /*16x ~ 32x gain*/
  559. coarse_again = 0x0f;
  560. coarse_dgain = 0x00;
  561. fine_dgain = gain_factor * 128 / 1000 / 16;
  562. //open dgain begin max digital gain 4X
  563. } else if (gain_factor < 1000 * 64) { /*32x ~ 64x gain*/
  564. coarse_again = 0x1f;
  565. coarse_dgain = 0x00;
  566. fine_dgain = gain_factor * 128 / 1000 / 32;
  567. } else if (gain_factor < 1000 * 128) { /*64x ~ 128x gain*/
  568. coarse_again = 0x1f;
  569. coarse_dgain = 0x01;
  570. fine_dgain = gain_factor * 128 / 1000 / 64;
  571. } else { /*max 128x gain*/
  572. coarse_again = 0x1f;
  573. coarse_dgain = 0x03;
  574. fine_dgain = 0x80;
  575. }
  576. dev_dbg(&sc2210->client->dev,
  577. "total_gain: 0x%x, d_gain: 0x%x, d_fine_gain: 0x%x, c_gain: 0x%x\n",
  578. gain, coarse_dgain, fine_dgain, coarse_again);
  579. ret = sc2210_write_reg(sc2210->client,
  580. sc2210_REG_DIG_GAIN,
  581. sc2210_REG_VALUE_08BIT,
  582. coarse_dgain);
  583. ret |= sc2210_write_reg(sc2210->client,
  584. sc2210_REG_DIG_FINE_GAIN,
  585. sc2210_REG_VALUE_08BIT,
  586. fine_dgain);
  587. ret |= sc2210_write_reg(sc2210->client,
  588. sc2210_REG_ANA_GAIN,
  589. sc2210_REG_VALUE_08BIT,
  590. coarse_again);
  591. return ret;
  592. }
  593. static int sc2210_get_reso_dist(const struct sc2210_mode *mode,
  594. struct v4l2_mbus_framefmt *framefmt)
  595. {
  596. return abs(mode->width - framefmt->width) +
  597. abs(mode->height - framefmt->height);
  598. }
  599. static const struct sc2210_mode *
  600. sc2210_find_best_fit(struct v4l2_subdev_format *fmt)
  601. {
  602. struct v4l2_mbus_framefmt *framefmt = &fmt->format;
  603. int dist;
  604. int cur_best_fit = 0;
  605. int cur_best_fit_dist = -1;
  606. unsigned int i;
  607. for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
  608. dist = sc2210_get_reso_dist(&supported_modes[i], framefmt);
  609. if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
  610. cur_best_fit_dist = dist;
  611. cur_best_fit = i;
  612. }
  613. }
  614. return &supported_modes[cur_best_fit];
  615. }
  616. static int sc2210_set_fmt(struct v4l2_subdev *sd,
  617. struct v4l2_subdev_pad_config *cfg,
  618. struct v4l2_subdev_format *fmt)
  619. {
  620. struct sc2210 *sc2210 = to_sc2210(sd);
  621. const struct sc2210_mode *mode;
  622. struct device *dev = &sc2210->client->dev;
  623. s64 h_blank, vblank_def;
  624. u64 dst_link_freq = 0;
  625. u64 dst_pixel_rate = 0;
  626. dev_info(dev,"enter sc2210_set_fmt\n");
  627. mutex_lock(&sc2210->mutex);
  628. mode = sc2210_find_best_fit(fmt);
  629. fmt->format.code = mode->bus_fmt;
  630. fmt->format.width = mode->width;
  631. fmt->format.height = mode->height;
  632. fmt->format.field = V4L2_FIELD_NONE;
  633. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  634. dev_info(dev,"enter v4l2_subdev_get_try_format\n");
  635. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  636. *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
  637. #else
  638. mutex_unlock(&sc2210->mutex);
  639. return -ENOTTY;
  640. #endif
  641. } else {
  642. sc2210->cur_mode = mode;
  643. h_blank = mode->hts_def - mode->width;
  644. __v4l2_ctrl_modify_range(sc2210->hblank, h_blank,
  645. h_blank, 1, h_blank);
  646. vblank_def = mode->vts_def - mode->height;
  647. __v4l2_ctrl_modify_range(sc2210->vblank, vblank_def,
  648. sc2210_VTS_MAX - mode->height,
  649. 1, vblank_def);
  650. dst_link_freq = mode->link_freq_idx;
  651. dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
  652. sc2210_BITS_PER_SAMPLE * 2 * sc2210_LANES;
  653. __v4l2_ctrl_s_ctrl_int64(sc2210->pixel_rate,
  654. dst_pixel_rate);
  655. __v4l2_ctrl_s_ctrl(sc2210->link_freq,
  656. dst_link_freq);
  657. dev_info(dev,"h_blank=%lld vblank_def=%lld dst_link_freq=%lld dst_pixel_rate=%lld\n",h_blank,vblank_def,dst_link_freq,dst_pixel_rate);
  658. }
  659. mutex_unlock(&sc2210->mutex);
  660. return 0;
  661. }
  662. static int sc2210_get_fmt(struct v4l2_subdev *sd,
  663. struct v4l2_subdev_pad_config *cfg,
  664. struct v4l2_subdev_format *fmt)
  665. {
  666. struct sc2210 *sc2210 = to_sc2210(sd);
  667. const struct sc2210_mode *mode = sc2210->cur_mode;
  668. mutex_lock(&sc2210->mutex);
  669. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  670. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  671. fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
  672. #else
  673. mutex_unlock(&sc2210->mutex);
  674. return -ENOTTY;
  675. #endif
  676. } else {
  677. fmt->format.width = mode->width;
  678. fmt->format.height = mode->height;
  679. fmt->format.code = mode->bus_fmt;
  680. fmt->format.field = V4L2_FIELD_NONE;
  681. /* format info: width/height/data type/virctual channel */
  682. if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
  683. fmt->reserved[0] = mode->vc[fmt->pad];
  684. else
  685. fmt->reserved[0] = mode->vc[PAD0];
  686. }
  687. mutex_unlock(&sc2210->mutex);
  688. return 0;
  689. }
  690. static int sc2210_enum_mbus_code(struct v4l2_subdev *sd,
  691. struct v4l2_subdev_pad_config *cfg,
  692. struct v4l2_subdev_mbus_code_enum *code)
  693. {
  694. struct sc2210 *sc2210 = to_sc2210(sd);
  695. if (code->index != 0)
  696. return -EINVAL;
  697. code->code = sc2210->cur_mode->bus_fmt;
  698. return 0;
  699. }
  700. static int sc2210_enum_frame_sizes(struct v4l2_subdev *sd,
  701. struct v4l2_subdev_pad_config *cfg,
  702. struct v4l2_subdev_frame_size_enum *fse)
  703. {
  704. if (fse->index >= ARRAY_SIZE(supported_modes))
  705. return -EINVAL;
  706. if (fse->code != supported_modes[0].bus_fmt)
  707. return -EINVAL;
  708. fse->min_width = supported_modes[fse->index].width;
  709. fse->max_width = supported_modes[fse->index].width;
  710. fse->max_height = supported_modes[fse->index].height;
  711. fse->min_height = supported_modes[fse->index].height;
  712. return 0;
  713. }
  714. static int sc2210_enable_test_pattern(struct sc2210 *sc2210, u32 pattern)
  715. {
  716. u32 val = 0;
  717. int ret = 0;
  718. ret = sc2210_read_reg(sc2210->client, sc2210_REG_TEST_PATTERN,
  719. sc2210_REG_VALUE_08BIT, &val);
  720. if (pattern)
  721. val |= sc2210_TEST_PATTERN_BIT_MASK;
  722. else
  723. val &= ~sc2210_TEST_PATTERN_BIT_MASK;
  724. ret |= sc2210_write_reg(sc2210->client, sc2210_REG_TEST_PATTERN,
  725. sc2210_REG_VALUE_08BIT, val);
  726. return ret;
  727. }
  728. static int sc2210_g_frame_interval(struct v4l2_subdev *sd,
  729. struct v4l2_subdev_frame_interval *fi)
  730. {
  731. struct sc2210 *sc2210 = to_sc2210(sd);
  732. const struct sc2210_mode *mode = sc2210->cur_mode;
  733. fi->interval = mode->max_fps;
  734. return 0;
  735. }
  736. static int sc2210_g_mbus_config(struct v4l2_subdev *sd,
  737. unsigned int pad_id,
  738. struct v4l2_mbus_config *config)
  739. {
  740. struct sc2210 *sc2210 = to_sc2210(sd);
  741. const struct sc2210_mode *mode = sc2210->cur_mode;
  742. u32 val = (1 << (sc2210_LANES - 1)) |
  743. V4L2_MBUS_CSI2_CHANNEL_0 |
  744. V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK; // V4L2_MBUS_CSI2_CONTINUOUS_CLOCK
  745. // if (mode->hdr_mode != NO_HDR)
  746. // val |= V4L2_MBUS_CSI2_CHANNEL_1;
  747. // if (mode->hdr_mode == HDR_X3)
  748. // val |= V4L2_MBUS_CSI2_CHANNEL_2;
  749. config->type = V4L2_MBUS_CSI2_DPHY;
  750. config->flags = val;
  751. printk("sc2210_g_mbus_config val=0x%X hdr_mode=%d\n",val,mode->hdr_mode );
  752. return 0;
  753. }
  754. static void sc2210_get_module_inf(struct sc2210 *sc2210,
  755. struct rkmodule_inf *inf)
  756. {
  757. memset(inf, 0, sizeof(*inf));
  758. strscpy(inf->base.sensor, sc2210_NAME, sizeof(inf->base.sensor));
  759. strscpy(inf->base.module, sc2210->module_name,
  760. sizeof(inf->base.module));
  761. strscpy(inf->base.lens, sc2210->len_name, sizeof(inf->base.lens));
  762. }
  763. static long sc2210_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
  764. {
  765. struct sc2210 *sc2210 = to_sc2210(sd);
  766. struct rkmodule_hdr_cfg *hdr;
  767. u32 i, h, w;
  768. long ret = 0;
  769. u32 stream = 0;
  770. switch (cmd) {
  771. case RKMODULE_GET_MODULE_INFO:
  772. sc2210_get_module_inf(sc2210, (struct rkmodule_inf *)arg);
  773. break;
  774. case RKMODULE_GET_HDR_CFG:
  775. hdr = (struct rkmodule_hdr_cfg *)arg;
  776. hdr->esp.mode = HDR_NORMAL_VC;
  777. hdr->hdr_mode = sc2210->cur_mode->hdr_mode;
  778. break;
  779. case RKMODULE_SET_HDR_CFG:
  780. hdr = (struct rkmodule_hdr_cfg *)arg;
  781. w = sc2210->cur_mode->width;
  782. h = sc2210->cur_mode->height;
  783. for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
  784. if (w == supported_modes[i].width &&
  785. h == supported_modes[i].height &&
  786. supported_modes[i].hdr_mode == hdr->hdr_mode) {
  787. sc2210->cur_mode = &supported_modes[i];
  788. break;
  789. }
  790. }
  791. if (i == ARRAY_SIZE(supported_modes)) {
  792. dev_err(&sc2210->client->dev,
  793. "not find hdr mode:%d %dx%d config\n",
  794. hdr->hdr_mode, w, h);
  795. ret = -EINVAL;
  796. } else {
  797. w = sc2210->cur_mode->hts_def - sc2210->cur_mode->width;
  798. h = sc2210->cur_mode->vts_def - sc2210->cur_mode->height;
  799. __v4l2_ctrl_modify_range(sc2210->hblank, w, w, 1, w);
  800. __v4l2_ctrl_modify_range(sc2210->vblank, h,
  801. sc2210_VTS_MAX - sc2210->cur_mode->height, 1, h);
  802. }
  803. break;
  804. case PREISP_CMD_SET_HDRAE_EXP:
  805. break;
  806. case RKMODULE_SET_QUICK_STREAM:
  807. stream = *((u32 *)arg);
  808. if (stream)
  809. ret = sc2210_write_reg(sc2210->client, sc2210_REG_CTRL_MODE,
  810. sc2210_REG_VALUE_08BIT, sc2210_MODE_STREAMING);
  811. else
  812. ret = sc2210_write_reg(sc2210->client, sc2210_REG_CTRL_MODE,
  813. sc2210_REG_VALUE_08BIT, sc2210_MODE_SW_STANDBY);
  814. break;
  815. default:
  816. ret = -ENOIOCTLCMD;
  817. break;
  818. }
  819. return ret;
  820. }
  821. #ifdef CONFIG_COMPAT
  822. static long sc2210_compat_ioctl32(struct v4l2_subdev *sd,
  823. unsigned int cmd, unsigned long arg)
  824. {
  825. void __user *up = compat_ptr(arg);
  826. struct rkmodule_inf *inf;
  827. struct rkmodule_hdr_cfg *hdr;
  828. struct preisp_hdrae_exp_s *hdrae;
  829. long ret;
  830. u32 stream = 0;
  831. switch (cmd) {
  832. case RKMODULE_GET_MODULE_INFO:
  833. inf = kzalloc(sizeof(*inf), GFP_KERNEL);
  834. if (!inf) {
  835. ret = -ENOMEM;
  836. return ret;
  837. }
  838. ret = sc2210_ioctl(sd, cmd, inf);
  839. if (!ret) {
  840. if (copy_to_user(up, inf, sizeof(*inf)))
  841. ret = -EFAULT;
  842. }
  843. kfree(inf);
  844. break;
  845. case RKMODULE_GET_HDR_CFG:
  846. hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
  847. if (!hdr) {
  848. ret = -ENOMEM;
  849. return ret;
  850. }
  851. ret = sc2210_ioctl(sd, cmd, hdr);
  852. if (!ret) {
  853. if (copy_to_user(up, hdr, sizeof(*hdr)))
  854. ret = -EFAULT;
  855. }
  856. kfree(hdr);
  857. break;
  858. case RKMODULE_SET_HDR_CFG:
  859. hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
  860. if (!hdr) {
  861. ret = -ENOMEM;
  862. return ret;
  863. }
  864. ret = copy_from_user(hdr, up, sizeof(*hdr));
  865. if (!ret)
  866. ret = sc2210_ioctl(sd, cmd, hdr);
  867. else
  868. ret = -EFAULT;
  869. kfree(hdr);
  870. break;
  871. case PREISP_CMD_SET_HDRAE_EXP:
  872. hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
  873. if (!hdrae) {
  874. ret = -ENOMEM;
  875. return ret;
  876. }
  877. ret = copy_from_user(hdrae, up, sizeof(*hdrae));
  878. if (!ret)
  879. ret = sc2210_ioctl(sd, cmd, hdrae);
  880. else
  881. ret = -EFAULT;
  882. kfree(hdrae);
  883. break;
  884. case RKMODULE_SET_QUICK_STREAM:
  885. ret = copy_from_user(&stream, up, sizeof(u32));
  886. if (!ret)
  887. ret = sc2210_ioctl(sd, cmd, &stream);
  888. else
  889. ret = -EFAULT;
  890. break;
  891. default:
  892. ret = -ENOIOCTLCMD;
  893. break;
  894. }
  895. return ret;
  896. }
  897. #endif
  898. static int __sc2210_start_stream(struct sc2210 *sc2210)
  899. {
  900. int ret;
  901. if (!sc2210->is_thunderboot) {
  902. ret = sc2210_write_array(sc2210->client, sc2210->cur_mode->reg_list);
  903. if (ret)
  904. return ret;
  905. /* In case these controls are set before streaming */
  906. ret = __v4l2_ctrl_handler_setup(&sc2210->ctrl_handler);
  907. if (ret)
  908. return ret;
  909. if (sc2210->has_init_exp && sc2210->cur_mode->hdr_mode != NO_HDR) {
  910. ret = sc2210_ioctl(&sc2210->subdev, PREISP_CMD_SET_HDRAE_EXP,
  911. &sc2210->init_hdrae_exp);
  912. if (ret) {
  913. dev_err(&sc2210->client->dev,
  914. "init exp fail in hdr mode\n");
  915. return ret;
  916. }
  917. }
  918. }
  919. ret = sc2210_write_reg(sc2210->client, sc2210_REG_CTRL_MODE,
  920. sc2210_REG_VALUE_08BIT, sc2210_MODE_STREAMING);
  921. return ret;
  922. }
  923. static int __sc2210_stop_stream(struct sc2210 *sc2210)
  924. {
  925. sc2210->has_init_exp = false;
  926. if (sc2210->is_thunderboot) {
  927. sc2210->is_first_streamoff = true;
  928. pm_runtime_put(&sc2210->client->dev);
  929. }
  930. return sc2210_write_reg(sc2210->client, sc2210_REG_CTRL_MODE,
  931. sc2210_REG_VALUE_08BIT, sc2210_MODE_SW_STANDBY);
  932. }
  933. static int __sc2210_power_on(struct sc2210 *sc2210);
  934. static int sc2210_s_stream(struct v4l2_subdev *sd, int on)
  935. {
  936. struct sc2210 *sc2210 = to_sc2210(sd);
  937. struct i2c_client *client = sc2210->client;
  938. int ret = 0;
  939. mutex_lock(&sc2210->mutex);
  940. on = !!on;
  941. if (on == sc2210->streaming)
  942. goto unlock_and_return;
  943. if (on) {
  944. if (sc2210->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
  945. sc2210->is_thunderboot = false;
  946. __sc2210_power_on(sc2210);
  947. }
  948. ret = pm_runtime_get_sync(&client->dev);
  949. if (ret < 0) {
  950. pm_runtime_put_noidle(&client->dev);
  951. goto unlock_and_return;
  952. }
  953. ret = __sc2210_start_stream(sc2210);
  954. if (ret) {
  955. v4l2_err(sd, "start stream failed while write regs\n");
  956. pm_runtime_put(&client->dev);
  957. goto unlock_and_return;
  958. }
  959. } else {
  960. __sc2210_stop_stream(sc2210);
  961. pm_runtime_put(&client->dev);
  962. }
  963. sc2210->streaming = on;
  964. unlock_and_return:
  965. mutex_unlock(&sc2210->mutex);
  966. return ret;
  967. }
  968. static int sc2210_s_power(struct v4l2_subdev *sd, int on)
  969. {
  970. struct sc2210 *sc2210 = to_sc2210(sd);
  971. struct i2c_client *client = sc2210->client;
  972. int ret = 0;
  973. mutex_lock(&sc2210->mutex);
  974. /* If the power state is not modified - no work to do. */
  975. if (sc2210->power_on == !!on)
  976. goto unlock_and_return;
  977. if (on) {
  978. ret = pm_runtime_get_sync(&client->dev);
  979. if (ret < 0) {
  980. pm_runtime_put_noidle(&client->dev);
  981. goto unlock_and_return;
  982. }
  983. if (!sc2210->is_thunderboot) {
  984. printk("sc2210_write_array sc2210_linear_10_1920x1080_30fps_regs\n");
  985. ret = sc2210_write_array(sc2210->client, sc2210_linear_10_1920x1080_30fps_regs);
  986. if (ret) {
  987. v4l2_err(sd, "could not set init registers\n");
  988. pm_runtime_put_noidle(&client->dev);
  989. goto unlock_and_return;
  990. }
  991. }
  992. sc2210->power_on = true;
  993. } else {
  994. pm_runtime_put(&client->dev);
  995. sc2210->power_on = false;
  996. }
  997. unlock_and_return:
  998. mutex_unlock(&sc2210->mutex);
  999. return ret;
  1000. }
  1001. /* Calculate the delay in us by clock rate and clock cycles */
  1002. static inline u32 sc2210_cal_delay(u32 cycles, struct sc2210 *sc2210)
  1003. {
  1004. return DIV_ROUND_UP(cycles, sc2210->cur_mode->xvclk_freq / 1000 / 1000);
  1005. }
  1006. static int __sc2210_power_on(struct sc2210 *sc2210)
  1007. {
  1008. int ret;
  1009. u32 delay_us;
  1010. struct device *dev = &sc2210->client->dev;
  1011. if (!IS_ERR_OR_NULL(sc2210->pins_default)) {
  1012. ret = pinctrl_select_state(sc2210->pinctrl,
  1013. sc2210->pins_default);
  1014. if (ret < 0)
  1015. dev_err(dev, "could not set pins\n");
  1016. }
  1017. ret = clk_set_rate(sc2210->xvclk, sc2210->cur_mode->xvclk_freq);
  1018. if (ret < 0)
  1019. dev_warn(dev, "Failed to set xvclk rate (%dHz)\n", sc2210->cur_mode->xvclk_freq);
  1020. if (clk_get_rate(sc2210->xvclk) != sc2210->cur_mode->xvclk_freq)
  1021. dev_warn(dev, "xvclk mismatched, modes are based on %dHz\n",
  1022. sc2210->cur_mode->xvclk_freq);
  1023. ret = clk_prepare_enable(sc2210->xvclk);
  1024. if (ret < 0) {
  1025. dev_err(dev, "Failed to enable xvclk\n");
  1026. return ret;
  1027. }
  1028. if (sc2210->is_thunderboot)
  1029. return 0;
  1030. if (!IS_ERR(sc2210->reset_gpio))
  1031. gpiod_set_value_cansleep(sc2210->reset_gpio, 0);
  1032. ret = regulator_bulk_enable(sc2210_NUM_SUPPLIES, sc2210->supplies);
  1033. if (ret < 0) {
  1034. dev_err(dev, "Failed to enable regulators\n");
  1035. goto disable_clk;
  1036. }
  1037. if (!IS_ERR(sc2210->reset_gpio))
  1038. gpiod_set_value_cansleep(sc2210->reset_gpio, 1);
  1039. usleep_range(500, 1000);
  1040. if (!IS_ERR(sc2210->reset_gpio))
  1041. usleep_range(6000, 8000);
  1042. else
  1043. usleep_range(12000, 16000);
  1044. /* 8192 cycles prior to first SCCB transaction */
  1045. delay_us = sc2210_cal_delay(8192, sc2210);
  1046. usleep_range(delay_us, delay_us * 2);
  1047. return 0;
  1048. disable_clk:
  1049. clk_disable_unprepare(sc2210->xvclk);
  1050. return ret;
  1051. }
  1052. static void __sc2210_power_off(struct sc2210 *sc2210)
  1053. {
  1054. int ret;
  1055. struct device *dev = &sc2210->client->dev;
  1056. clk_disable_unprepare(sc2210->xvclk);
  1057. if (sc2210->is_thunderboot) {
  1058. if (sc2210->is_first_streamoff) {
  1059. sc2210->is_thunderboot = false;
  1060. sc2210->is_first_streamoff = false;
  1061. } else {
  1062. return;
  1063. }
  1064. }
  1065. if (!IS_ERR(sc2210->reset_gpio))
  1066. gpiod_set_value_cansleep(sc2210->reset_gpio, 0);
  1067. if (!IS_ERR_OR_NULL(sc2210->pins_sleep)) {
  1068. ret = pinctrl_select_state(sc2210->pinctrl,
  1069. sc2210->pins_sleep);
  1070. if (ret < 0)
  1071. dev_dbg(dev, "could not set pins\n");
  1072. }
  1073. regulator_bulk_disable(sc2210_NUM_SUPPLIES, sc2210->supplies);
  1074. }
  1075. static int sc2210_runtime_resume(struct device *dev)
  1076. {
  1077. struct i2c_client *client = to_i2c_client(dev);
  1078. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1079. struct sc2210 *sc2210 = to_sc2210(sd);
  1080. return __sc2210_power_on(sc2210);
  1081. }
  1082. static int sc2210_runtime_suspend(struct device *dev)
  1083. {
  1084. struct i2c_client *client = to_i2c_client(dev);
  1085. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1086. struct sc2210 *sc2210 = to_sc2210(sd);
  1087. __sc2210_power_off(sc2210);
  1088. return 0;
  1089. }
  1090. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1091. static int sc2210_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  1092. {
  1093. struct sc2210 *sc2210 = to_sc2210(sd);
  1094. struct v4l2_mbus_framefmt *try_fmt =
  1095. v4l2_subdev_get_try_format(sd, fh->pad, 0);
  1096. const struct sc2210_mode *def_mode = &supported_modes[0];
  1097. mutex_lock(&sc2210->mutex);
  1098. /* Initialize try_fmt */
  1099. try_fmt->width = def_mode->width;
  1100. try_fmt->height = def_mode->height;
  1101. try_fmt->code = def_mode->bus_fmt;
  1102. try_fmt->field = V4L2_FIELD_NONE;
  1103. mutex_unlock(&sc2210->mutex);
  1104. /* No crop or compose */
  1105. return 0;
  1106. }
  1107. #endif
  1108. static int sc2210_enum_frame_interval(struct v4l2_subdev *sd,
  1109. struct v4l2_subdev_pad_config *cfg,
  1110. struct v4l2_subdev_frame_interval_enum *fie)
  1111. {
  1112. if (fie->index >= ARRAY_SIZE(supported_modes))
  1113. return -EINVAL;
  1114. fie->code = supported_modes[fie->index].bus_fmt;
  1115. fie->width = supported_modes[fie->index].width;
  1116. fie->height = supported_modes[fie->index].height;
  1117. fie->interval = supported_modes[fie->index].max_fps;
  1118. fie->reserved[0] = supported_modes[fie->index].hdr_mode;
  1119. return 0;
  1120. }
  1121. static const struct dev_pm_ops sc2210_pm_ops = {
  1122. SET_RUNTIME_PM_OPS(sc2210_runtime_suspend,
  1123. sc2210_runtime_resume, NULL)
  1124. };
  1125. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1126. static const struct v4l2_subdev_internal_ops sc2210_internal_ops = {
  1127. .open = sc2210_open,
  1128. };
  1129. #endif
  1130. static const struct v4l2_subdev_core_ops sc2210_core_ops = {
  1131. .s_power = sc2210_s_power,
  1132. .ioctl = sc2210_ioctl,
  1133. #ifdef CONFIG_COMPAT
  1134. .compat_ioctl32 = sc2210_compat_ioctl32,
  1135. #endif
  1136. };
  1137. static const struct v4l2_subdev_video_ops sc2210_video_ops = {
  1138. .s_stream = sc2210_s_stream,
  1139. .g_frame_interval = sc2210_g_frame_interval,
  1140. };
  1141. static const struct v4l2_subdev_pad_ops sc2210_pad_ops = {
  1142. .enum_mbus_code = sc2210_enum_mbus_code,
  1143. .enum_frame_size = sc2210_enum_frame_sizes,
  1144. .enum_frame_interval = sc2210_enum_frame_interval,
  1145. .get_fmt = sc2210_get_fmt,
  1146. .set_fmt = sc2210_set_fmt,
  1147. .get_mbus_config = sc2210_g_mbus_config,
  1148. };
  1149. static const struct v4l2_subdev_ops sc2210_subdev_ops = {
  1150. .core = &sc2210_core_ops,
  1151. .video = &sc2210_video_ops,
  1152. .pad = &sc2210_pad_ops,
  1153. };
  1154. /// @brief
  1155. /// @param ctrl
  1156. /// @return
  1157. static int sc2210_set_ctrl(struct v4l2_ctrl *ctrl)
  1158. {
  1159. struct sc2210 *sc2210 = container_of(ctrl->handler,
  1160. struct sc2210, ctrl_handler);
  1161. struct i2c_client *client = sc2210->client;
  1162. s64 max;
  1163. int ret = 0;
  1164. u32 val = 0;
  1165. /* Propagate change of current control to all related controls */
  1166. switch (ctrl->id) {
  1167. case V4L2_CID_VBLANK:
  1168. /* Update max exposure while meeting expected vblanking */
  1169. max = sc2210->cur_mode->height + ctrl->val - 8;
  1170. __v4l2_ctrl_modify_range(sc2210->exposure,
  1171. sc2210->exposure->minimum, max,
  1172. sc2210->exposure->step,
  1173. sc2210->exposure->default_value);
  1174. break;
  1175. }
  1176. if (!pm_runtime_get_if_in_use(&client->dev))
  1177. return 0;
  1178. switch (ctrl->id) {
  1179. case V4L2_CID_EXPOSURE:
  1180. dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
  1181. if (sc2210->cur_mode->hdr_mode == NO_HDR) {
  1182. val = ctrl->val;
  1183. // // /* 4 least significant bits of expsoure are fractional part */
  1184. ret = sc2210_write_reg(sc2210->client,
  1185. sc2210_REG_EXPOSURE_H,
  1186. sc2210_REG_VALUE_08BIT,
  1187. sc2210_FETCH_EXP_H(val));
  1188. ret |= sc2210_write_reg(sc2210->client,
  1189. sc2210_REG_EXPOSURE_M,
  1190. sc2210_REG_VALUE_08BIT,
  1191. sc2210_FETCH_EXP_M(val));
  1192. ret |= sc2210_write_reg(sc2210->client,
  1193. sc2210_REG_EXPOSURE_L,
  1194. sc2210_REG_VALUE_08BIT,
  1195. sc2210_FETCH_EXP_L(val));
  1196. }
  1197. break;
  1198. case V4L2_CID_ANALOGUE_GAIN:
  1199. dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
  1200. if (sc2210->cur_mode->hdr_mode == NO_HDR)
  1201. ret = sc2210_set_gain_reg(sc2210, ctrl->val);
  1202. break;
  1203. case V4L2_CID_VBLANK:
  1204. dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
  1205. ret = sc2210_write_reg(sc2210->client,
  1206. sc2210_REG_VTS_H,
  1207. sc2210_REG_VALUE_08BIT,
  1208. (ctrl->val + sc2210->cur_mode->height)
  1209. >> 8);
  1210. ret |= sc2210_write_reg(sc2210->client,
  1211. sc2210_REG_VTS_L,
  1212. sc2210_REG_VALUE_08BIT,
  1213. (ctrl->val + sc2210->cur_mode->height)
  1214. & 0xff);
  1215. sc2210->cur_vts = ctrl->val + sc2210->cur_mode->height;
  1216. break;
  1217. case V4L2_CID_TEST_PATTERN:
  1218. ret = sc2210_enable_test_pattern(sc2210, ctrl->val);
  1219. break;
  1220. case V4L2_CID_HFLIP:
  1221. ret = sc2210_read_reg(sc2210->client, sc2210_FLIP_MIRROR_REG,
  1222. sc2210_REG_VALUE_08BIT, &val);
  1223. ret |= sc2210_write_reg(sc2210->client, sc2210_FLIP_MIRROR_REG,
  1224. sc2210_REG_VALUE_08BIT,
  1225. sc2210_FETCH_MIRROR(val, ctrl->val));
  1226. break;
  1227. case V4L2_CID_VFLIP:
  1228. ret = sc2210_read_reg(sc2210->client, sc2210_FLIP_MIRROR_REG,
  1229. sc2210_REG_VALUE_08BIT, &val);
  1230. ret |= sc2210_write_reg(sc2210->client, sc2210_FLIP_MIRROR_REG,
  1231. sc2210_REG_VALUE_08BIT,
  1232. sc2210_FETCH_FLIP(val, ctrl->val));
  1233. break;
  1234. default:
  1235. dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
  1236. __func__, ctrl->id, ctrl->val);
  1237. break;
  1238. }
  1239. pm_runtime_put(&client->dev);
  1240. return ret;
  1241. }
  1242. static const struct v4l2_ctrl_ops sc2210_ctrl_ops = {
  1243. .s_ctrl = sc2210_set_ctrl,
  1244. };
  1245. static int sc2210_initialize_controls(struct sc2210 *sc2210)
  1246. {
  1247. const struct sc2210_mode *mode;
  1248. struct v4l2_ctrl_handler *handler;
  1249. struct device *dev = &sc2210->client->dev;
  1250. s64 exposure_max, vblank_def;
  1251. u32 h_blank;
  1252. int ret;
  1253. u64 dst_link_freq = 0;
  1254. u64 dst_pixel_rate = 0;
  1255. handler = &sc2210->ctrl_handler;
  1256. mode = sc2210->cur_mode;
  1257. ret = v4l2_ctrl_handler_init(handler, 9);
  1258. if (ret)
  1259. return ret;
  1260. handler->lock = &sc2210->mutex;
  1261. sc2210->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
  1262. V4L2_CID_LINK_FREQ,
  1263. ARRAY_SIZE(link_freq_menu_items) - 1, 0, link_freq_menu_items);
  1264. if (sc2210->link_freq)
  1265. sc2210->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  1266. dst_link_freq = mode->link_freq_idx;
  1267. dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
  1268. sc2210_BITS_PER_SAMPLE * 2 * sc2210_LANES;
  1269. sc2210->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
  1270. 0, PIXEL_RATE_WITH_405M_10BIT, 1, dst_pixel_rate);
  1271. __v4l2_ctrl_s_ctrl(sc2210->link_freq, dst_link_freq);
  1272. h_blank = mode->hts_def - mode->width;
  1273. sc2210->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
  1274. h_blank, h_blank, 1, h_blank);
  1275. if (sc2210->hblank)
  1276. sc2210->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  1277. vblank_def = mode->vts_def - mode->height;
  1278. sc2210->vblank = v4l2_ctrl_new_std(handler, &sc2210_ctrl_ops,
  1279. V4L2_CID_VBLANK, vblank_def,
  1280. sc2210_VTS_MAX - mode->height,
  1281. 1, vblank_def);
  1282. exposure_max = mode->vts_def - 8;
  1283. sc2210->exposure = v4l2_ctrl_new_std(handler, &sc2210_ctrl_ops,
  1284. V4L2_CID_EXPOSURE, sc2210_EXPOSURE_MIN,
  1285. exposure_max, sc2210_EXPOSURE_STEP,
  1286. mode->exp_def);
  1287. sc2210->anal_gain = v4l2_ctrl_new_std(handler, &sc2210_ctrl_ops,
  1288. V4L2_CID_ANALOGUE_GAIN, sc2210_GAIN_MIN,
  1289. sc2210_GAIN_MAX, sc2210_GAIN_STEP,
  1290. sc2210_GAIN_DEFAULT);
  1291. sc2210->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
  1292. &sc2210_ctrl_ops,
  1293. V4L2_CID_TEST_PATTERN,
  1294. ARRAY_SIZE(sc2210_test_pattern_menu) - 1,
  1295. 0, 0, sc2210_test_pattern_menu);
  1296. v4l2_ctrl_new_std(handler, &sc2210_ctrl_ops,
  1297. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1298. v4l2_ctrl_new_std(handler, &sc2210_ctrl_ops,
  1299. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1300. if (handler->error) {
  1301. ret = handler->error;
  1302. dev_err(&sc2210->client->dev,
  1303. "Failed to init controls(%d)\n", ret);
  1304. goto err_free_handler;
  1305. }
  1306. sc2210->subdev.ctrl_handler = handler;
  1307. sc2210->has_init_exp = false;
  1308. dev_info(dev,"sc2210_initialize_controls \n");
  1309. return 0;
  1310. err_free_handler:
  1311. v4l2_ctrl_handler_free(handler);
  1312. return ret;
  1313. }
  1314. static int sc2210_check_sensor_id(struct sc2210 *sc2210,
  1315. struct i2c_client *client)
  1316. {
  1317. struct device *dev = &sc2210->client->dev;
  1318. u32 id = 0;
  1319. int ret;
  1320. if (sc2210->is_thunderboot) {
  1321. dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
  1322. return 0;
  1323. }
  1324. ret = sc2210_read_reg(client, sc2210_REG_CHIP_ID,
  1325. sc2210_REG_VALUE_16BIT, &id);
  1326. if (id != CHIP_ID) {
  1327. dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
  1328. return -ENODEV;
  1329. }
  1330. dev_info(dev, "Detected SC%06x sensor\n", CHIP_ID);
  1331. return 0;
  1332. }
  1333. static int sc2210_configure_regulators(struct sc2210 *sc2210)
  1334. {
  1335. unsigned int i;
  1336. for (i = 0; i < sc2210_NUM_SUPPLIES; i++)
  1337. sc2210->supplies[i].supply = sc2210_supply_names[i];
  1338. return devm_regulator_bulk_get(&sc2210->client->dev,
  1339. sc2210_NUM_SUPPLIES,
  1340. sc2210->supplies);
  1341. }
  1342. static int sc2210_probe(struct i2c_client *client,
  1343. const struct i2c_device_id *id)
  1344. {
  1345. struct device *dev = &client->dev;
  1346. struct device_node *node = dev->of_node;
  1347. struct sc2210 *sc2210;
  1348. struct v4l2_subdev *sd;
  1349. char facing[2];
  1350. int ret;
  1351. int i, hdr_mode = 0;
  1352. dev_info(dev, "driver version: %02x.%02x.%02x",
  1353. DRIVER_VERSION >> 16,
  1354. (DRIVER_VERSION & 0xff00) >> 8,
  1355. DRIVER_VERSION & 0x00ff);
  1356. sc2210 = devm_kzalloc(dev, sizeof(*sc2210), GFP_KERNEL);
  1357. if (!sc2210)
  1358. return -ENOMEM;
  1359. ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
  1360. &sc2210->module_index);
  1361. ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
  1362. &sc2210->module_facing);
  1363. ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
  1364. &sc2210->module_name);
  1365. ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
  1366. &sc2210->len_name);
  1367. if (ret) {
  1368. dev_err(dev, "could not get module information!\n");
  1369. return -EINVAL;
  1370. }
  1371. sc2210->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
  1372. sc2210->client = client;
  1373. for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
  1374. if (hdr_mode == supported_modes[i].hdr_mode) {
  1375. sc2210->cur_mode = &supported_modes[i];
  1376. break;
  1377. }
  1378. }
  1379. if (i == ARRAY_SIZE(supported_modes))
  1380. sc2210->cur_mode = &supported_modes[0];
  1381. sc2210->xvclk = devm_clk_get(dev, "xvclk");
  1382. if (IS_ERR(sc2210->xvclk)) {
  1383. dev_err(dev, "Failed to get xvclk\n");
  1384. return -EINVAL;
  1385. }
  1386. if (sc2210->is_thunderboot) {
  1387. sc2210->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
  1388. if (IS_ERR(sc2210->reset_gpio))
  1389. dev_warn(dev, "Failed to get reset-gpios\n");
  1390. } else {
  1391. sc2210->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
  1392. if (IS_ERR(sc2210->reset_gpio))
  1393. dev_warn(dev, "Failed to get reset-gpios\n");
  1394. }
  1395. sc2210->pinctrl = devm_pinctrl_get(dev);
  1396. if (!IS_ERR(sc2210->pinctrl)) {
  1397. sc2210->pins_default =
  1398. pinctrl_lookup_state(sc2210->pinctrl,
  1399. OF_CAMERA_PINCTRL_STATE_DEFAULT);
  1400. if (IS_ERR(sc2210->pins_default))
  1401. dev_err(dev, "could not get default pinstate\n");
  1402. sc2210->pins_sleep =
  1403. pinctrl_lookup_state(sc2210->pinctrl,
  1404. OF_CAMERA_PINCTRL_STATE_SLEEP);
  1405. if (IS_ERR(sc2210->pins_sleep))
  1406. dev_err(dev, "could not get sleep pinstate\n");
  1407. } else {
  1408. dev_err(dev, "no pinctrl\n");
  1409. }
  1410. ret = sc2210_configure_regulators(sc2210);
  1411. if (ret) {
  1412. dev_err(dev, "Failed to get power regulators\n");
  1413. return ret;
  1414. }
  1415. mutex_init(&sc2210->mutex);
  1416. sd = &sc2210->subdev;
  1417. v4l2_i2c_subdev_init(sd, client, &sc2210_subdev_ops);
  1418. ret = sc2210_initialize_controls(sc2210);
  1419. if (ret)
  1420. goto err_destroy_mutex;
  1421. ret = __sc2210_power_on(sc2210);
  1422. if (ret)
  1423. goto err_free_handler;
  1424. ret = sc2210_check_sensor_id(sc2210, client);
  1425. if (ret)
  1426. goto err_power_off;
  1427. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1428. sd->internal_ops = &sc2210_internal_ops;
  1429. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
  1430. V4L2_SUBDEV_FL_HAS_EVENTS;
  1431. #endif
  1432. #if defined(CONFIG_MEDIA_CONTROLLER)
  1433. sc2210->pad.flags = MEDIA_PAD_FL_SOURCE;
  1434. sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
  1435. ret = media_entity_pads_init(&sd->entity, 1, &sc2210->pad);
  1436. if (ret < 0)
  1437. goto err_power_off;
  1438. #endif
  1439. memset(facing, 0, sizeof(facing));
  1440. if (strcmp(sc2210->module_facing, "back") == 0)
  1441. facing[0] = 'b';
  1442. else
  1443. facing[0] = 'f';
  1444. snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
  1445. sc2210->module_index, facing,
  1446. sc2210_NAME, dev_name(sd->dev));
  1447. ret = v4l2_async_register_subdev_sensor_common(sd);
  1448. if (ret) {
  1449. dev_err(dev, "v4l2 async register subdev failed\n");
  1450. goto err_clean_entity;
  1451. }
  1452. pm_runtime_set_active(dev);
  1453. pm_runtime_enable(dev);
  1454. if (sc2210->is_thunderboot)
  1455. pm_runtime_get_sync(dev);
  1456. else
  1457. pm_runtime_idle(dev);
  1458. return 0;
  1459. err_clean_entity:
  1460. #if defined(CONFIG_MEDIA_CONTROLLER)
  1461. media_entity_cleanup(&sd->entity);
  1462. #endif
  1463. err_power_off:
  1464. __sc2210_power_off(sc2210);
  1465. err_free_handler:
  1466. v4l2_ctrl_handler_free(&sc2210->ctrl_handler);
  1467. err_destroy_mutex:
  1468. mutex_destroy(&sc2210->mutex);
  1469. return ret;
  1470. }
  1471. static int sc2210_remove(struct i2c_client *client)
  1472. {
  1473. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1474. struct sc2210 *sc2210 = to_sc2210(sd);
  1475. v4l2_async_unregister_subdev(sd);
  1476. #if defined(CONFIG_MEDIA_CONTROLLER)
  1477. media_entity_cleanup(&sd->entity);
  1478. #endif
  1479. v4l2_ctrl_handler_free(&sc2210->ctrl_handler);
  1480. mutex_destroy(&sc2210->mutex);
  1481. pm_runtime_disable(&client->dev);
  1482. if (!pm_runtime_status_suspended(&client->dev))
  1483. __sc2210_power_off(sc2210);
  1484. pm_runtime_set_suspended(&client->dev);
  1485. return 0;
  1486. }
  1487. #if IS_ENABLED(CONFIG_OF)
  1488. static const struct of_device_id sc2210_of_match[] = {
  1489. { .compatible = "smartsens,sc2210" },
  1490. {},
  1491. };
  1492. MODULE_DEVICE_TABLE(of, sc2210_of_match);
  1493. #endif
  1494. static const struct i2c_device_id sc2210_match_id[] = {
  1495. { "smartsens,sc2210", 0 },
  1496. { },
  1497. };
  1498. static struct i2c_driver sc2210_i2c_driver = {
  1499. .driver = {
  1500. .name = sc2210_NAME,
  1501. .pm = &sc2210_pm_ops,
  1502. .of_match_table = of_match_ptr(sc2210_of_match),
  1503. },
  1504. .probe = &sc2210_probe,
  1505. .remove = &sc2210_remove,
  1506. .id_table = sc2210_match_id,
  1507. };
  1508. static int __init sensor_mod_init(void)
  1509. {
  1510. return i2c_add_driver(&sc2210_i2c_driver);
  1511. }
  1512. static void __exit sensor_mod_exit(void)
  1513. {
  1514. i2c_del_driver(&sc2210_i2c_driver);
  1515. }
  1516. #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
  1517. subsys_initcall(sensor_mod_init);
  1518. #else
  1519. device_initcall_sync(sensor_mod_init);
  1520. #endif
  1521. module_exit(sensor_mod_exit);
  1522. MODULE_DESCRIPTION("smartsens sc2210 sensor driver");
  1523. MODULE_LICENSE("GPL");